Hybrid Multi-Die Architecture
Get the most I/O and memory bandwidth (double-digit gains in estimated instructions per second) in its class with ZEN 5 Core and ZEN 5c core
- Decoupled Innovation Paths: 4nm technology for Zen 5 cores and 3nm technology for Zen 5c cores. While the I/O die remains at 6nm from prior generation
- Modular approach to mix and match CCPU and I/O dies to create specialized CPUs to match with workload requirements (from 8-Cores upto 192 Cores)
- Zen 5 core optimized for high performance: 8-Cores to create core complex (CCX) including a 32MB shared L3 cache. This is fabricated to a die (CCD) and upto 16 of these can be configured in a single SP5 CPU, total of 128 cores.
- Zen 5 core: 20% greater integer, 30% greater floating-point performance compared to previous same 360W TDP range.
- Zen 5c Core optimized for density and efficiency: with physical layout takes less space and deliver more performance per watt
- Zen 5c CCD includes 16 cores and shared 32MB L3 Cache, 12 of which can be combined with I/O CCD for CPUs with 192 cores in SP5 form factor.
I/O Bandwidth Leader
Support for CXL2.0 + Memory (CXL Type 1 and Type 3) - 128 lanes for 1P and 160 lanes for 2P, 128 PCIe gen 5 lanes
- AMD Infinity Fabric for interprocessor communication in 2P. Different protocols layered on physical (PHY) layer to support 3-4 links each 32Gb/s x16 PCIe speeds.
- I/O serializer-deserializer (SERDES) logic: one set of traces programmable to support multiple functions.
- Idealized Bifurcation with no single SERDES providing all of them. Entire 16-lane port can be dedicated to Infinity Fabric, PCIe or CXL connecitity.
- PCIe can be broken down to x8, x4, x2 and x1 bandwidth. CXL connections can have x16, x8, or x4 bandwidth.
- 12 Channels of DDR-6000 memory - Upto 6TB memory with enhanced single-rank performance
- Max Data Bandwidth doubled between core and 48 KB L1 data cache.
- Internal Infinity Fabric Interfaces connect I/O die with each CPU die using 16 36Gbp/s links. 72Gb/s of connectivity. Bandwidth per link: total 576GB/s per socket
- With 128 lanes in a Single Socket, upto 160 lanes in a Dual Socket Configuration.
- Improved execution pipelines, higher clock rates, and up to 6TB DDR5 memory capacity
- Compared to prior gen: ~37% geometric mean on ML and HPC workloads and ~17% geometric mean on enterprise workloads
Advanced Security
Get AMD Infinity Guard - Modern ZEN architecture with Broad Ecosystem Support
- Core Level Security - tagging of memory to threads when read into the processor caches. The option for one guest operating systems in virtualized environmentsto run exclusively on one core - to protect against side-channel attacks targeted at cached memory.
- Transparent Secure Memory Encryption (TSME): AES-XTS 256-bit Encryption Engines built into the memory controllers (128- or 256-bit keys)
- Secure Memory Encryption (SME), and
- 512 Threads (upto 1006 keys for) Secure Encrypted Virtualization (SEV) for protection against untrusted hypervisor.
- Hardware-validated boot helps verify that the OS or hypervisor software that is intended to load is what is actually loaded. The AMD Secure Processor loads on-chip boot ROM that loads and authenticates the BIOS before any "Zen" core can execute the code.
- Isolate memory within the CPU so that the active thread can access memory only assigned to that thread
SEV, SEV-ES, SEV-SNP, SMKE and Trusted I/O
Encrypt the contents of main memory with simple change in BIOS setting. 256-bit encryption engines are built into memory controllers to help reduce performance impact.
- Cryptographically isolate each VM with a unique key that is known only to the processor with up to 509 contexts
- Protect confidentiality of data even if a malicious VM finds a way into your VM's memory or if compromised hypervisor reaches guest VM
- AMD Secure Encrypted State (SEV-ES): Encrypt VM state when interrupts cause it to be stored in the hypervisor. A compromised hypervisor will still be unable to view VM's registers.
- SEV-SNP, AMD Secure Nested Paging - adds strong encryption to VM nested page tables to prevent various attacks - creating confidential, isolated execution environment for VMs.
- With SEV-SNP, hypervisors can also use third-party encryption keys for attesting guest VMs. Attestation may include measurements of trusted computing base.
- The secure multi-key encryption (SMKE) enables hypervisors to selectively encrypt address space ranges on CXL-attached memory even across a system reboot.
- AMD Trusted I/O establishes a framework for securing virtualized I/O paths. Supports the PCI-SIG TDISP standard that mutually authenticates VM and device before establishing an encrypted connection.
The Value Leader
Save more with affordable AMD EPYC 5th Gen Turin CPU Servers from HostCircle B.V.
- Simplified Production: Hybird Multi-Die Architecture help reduce waste in fabrication process. Reducing overall yield in terms of avg number of processors produced per wafer. Thus reducing costs.
- Small, Fast, Low-Power transistors for power efficiency and higher performance
- Quality Bandwidth at affordable pricing. 40Gbps and 100Gbps servers as standard.
- Server racked and stacked in enterprise datacenters only. Best Environment for Best Performance.
- The usual: Redundant network with Quick Support 24x7
